1. Field of the Invention
This disclosure relates to a semiconductor memory device, and more particularly, to a method of manufacturing a recess type MOS transistor, from which a refresh characteristic can be improved through an impurity region having a dual diode structure.
2. Description of the Related Art
MOS (Metal-Oxide Semiconductor) devices are increasingly miniaturized in response to the desire to increase the integration of semiconductor devices. Channel lengths are reduced to the deep sub-micron level in order to increase an operating speed and current drive capability of the device.
According to the gradual reduction of channel length, source and drain depletion regions may invade the channel, causing a reduction to the effective channel length and the threshold voltage. This causes a short channel effect that may cause a gate control function to be lost in a MOS transistor.
In order to reduce these short channel effects, a conductive dopant may be ion-implanted into a lower part of the gate region, the conductive dopant having a conductivity type opposite to that of a conductive impurity doped in the source/drain regions. However, when a high electric field is applied in such a semiconductor device, a hot carrier effect may occur. The hot carrier again generates collision ionization so that the hot carrier invades into an oxide layer, that is, the oxide layer is degraded with a defect of the device.
To reduce the hot carrier effect, most transistor manufacturing processes employ an LDD (Lightly Doped Drain) structure, and this produces a buffer region of low density between the gate region and a drain region of low density.
In the meantime, a continuous requirement for a high integration of semiconductor device makes the channel length be shorter, thus the transistor of the LDD structure also has a limitation in reducing the short channel effect and the hot carrier effect. Furthermore, there is caused a punchthrough effect when the source and drain impurities diffuse toward side faces during operation of the transistor.
To solve the above problems and to further reduce a size of high-density memory cells formed inside a semiconductor substrate, there is a requirement to develop a transistor having a recessed or grooved channel based on more lengthened channel-length instead of a planar-type per unit area.
The recess-type MOS transistor increases an effective channel length by forming a trench in a region where a channel will be formed, to thus improve a punchthrough of source and drain regions and actually extend a distance between the source and drain regions so as to be consequently helpful for a high integration of semiconductor device.
FIGS. 1A to 1J are cross-sectional diagrams illustrating a conventional method of manufacturing a recess-type MOS transistor.
As shown in FIG. 1A, a first pad oxide layer 12 and a second hard mask layer 14 are sequentially formed on a semiconductor substrate 10.
As shown in FIG. 1B, photoresist is deposited on the first hard mask layer 14, and is then patterned to partially expose the hard mask layer 14. The first hard mask layer 14 is etched to expose the first pad oxide layer 12 by using the photoresist as an etch mask, to thus define an active region ACT. Then the photoresist is removed.
In FIG. 1C, the first pad oxide layer 12 and a portion of the semiconductor substrate 10 are sequentially removed by using the first hard mask layer 14 as an etch mask, to thus form a first trench T1 inside the semiconductor substrate 10.
In FIG. 1D, a device isolation film 16 is formed within the first trench T1 through a thermal oxidation process by using the first hard mask layer 14 or the first pad oxide layer as an oxidation prevention mask. All the first hard mask layer 14 and the first pad oxide layer 12 are removed by a chemical mechanical polishing (CMP) or etch back process, to partially expose the semiconductor substrate 10 on which the device isolation film 16 was formed. That is, the semiconductor substrate 10 is planarized.
In FIG. 1E, a P-type impurity is ion implanted with a low density at high energy into the semiconductor substrate 10 on which the device isolation film 16 was formed, to form a channel impurity region. With the exception of the portion of the semiconductor substrate occupied by the device isolation film 16, the channel impurity region is formed on the semiconductor substrate 10. Thus, the channel impurity region does not have a specific reference character or number in the drawings. In the active region ACT of the semiconductor substrate 10 on which the channel impurity region was formed, an N-type impurity is ion implanted, to form a third impurity region 17 having a predetermined depth from the surface.
In FIG. 1F, a second pad oxide layer 18 and a second hard mask layer 20 are sequentially accumulated on the semiconductor substrate 10 on which the third impurity region 17 was formed.
In FIG. 1G, photoresist is deposited on the semiconductor substrate 10 where the second hard mask layer 20 was formed, and is patterned through a photolithography process. Then, the second hard mask layer 20 is etched to expose the second pad oxide layer 18 by using the photoresist as an etch mask. Next, the photoresist is removed.
In FIG. 1H, the second pad oxide layer 18 and the semiconductor substrate 10 are sequentially etched by using the second hard mask layer 20 as an etch mask, to thus form a second trench T2 having a predetermined depth. A sidewall of the second trench T2 of the semiconductor substrate 10 is partially removed to isolate between a source region S and a drain region D.
In FIG. 1I, the second hard mask layer 20 and the second pad oxide layer 18, which were formed on the semiconductor substrate 12, are removed to expose the surface of the semiconductor substrate 10 and the device isolation film 16.
In FIG. 1J, a gate insulation layer 22 is formed on the semiconductor substrate 10 including the second trench T2.
In FIG. 1K, a gate electrode 24, a metal layer 26, and a gate upper insulation layer 28 are sequentially formed on the semiconductor substrate 10 on which the gate insulation layer 22 was formed.
In FIG. 1L, photoresist is deposited on an entire face of the semiconductor substrate 10 on which the gate upper insulation layer 28 was formed, and is then patterned through a photolithography process. The gate upper insulation layer 28, the metal layer 26, and the gate electrode 24 formed on the source/drain regions S/D and a portion of the device isolation film 16 are sequentially removed to form a gate stack 30 on a gate region G. Subsequently, an N-type impurity may be implanted at a low density in the semiconductor substrate of the source/drain regions S/D by using the gate stack 30 as an ion implantation mask, so as to form the third impurity region 17 in the source/drain regions S/D.
In FIG. 1M, a silicon nitride layer is formed on the semiconductor substrate 10 where the gate stack 30 was formed, and is then removed through a dry etching method having a prominent vertical characteristic, to form a spacer 34 in a sidewall of the gate stack.
In FIG. 1N, the N-type impurity is ion implanted at a high density in the semiconductor substrate 10 of the source/drain regions S/D by using the gate upper insulation layer 28 and the spacer 34 as an ion implantation mask, to thus form a fifth impurity region 36.
In FIG. 1O, the gate insulation layer 22 is removed from an upper part of the source/drain regions S/D of the semiconductor substrate 10 on which the fifth impurity region 36 was formed.
In FIG. 1P, an N-type impurity or polysilicon layer containing the N-type impurity is formed on the semiconductor substrate 10, and photoresist is deposited on the polysilicon layer, and is then patterned through a photolithography process. Next, the polysilicon layer is etched by using the photoresist as an etch mask, to form source/drain electrodes 38 (hereinafter, referred to as “pad polysilicon layer”).
Subsequently, a first interlayer insulation layer is formed on the semiconductor substrate 10 on which the pad polysilicon layer 38 was formed, and is then removed from an upper part of the source region S, to form a first contact hole. Next, a bit line contact electrically coupled with the pad polysilicon layer 38 through the first contact hole is formed, and a second interlayer insulation layer is formed on the semiconductor substrate 10 including the bit line contact. The first and second interlayer insulation layers are removed from an upper part of the drain region D, to form a second contact hole. Thereon, a storage electrode, a dielectric layer and a plate electrode, which are electrically coupled with the pad polysilicon layer 38 through the second contact hole, are sequentially formed, completing a capacitor of a memory cell.
In the recess type MOS transistor manufactured according to the method described above, data applied to the bit line is stored in the memory cell capacitor by a gate voltage applied to the gate electrode 24, and then the data stored in the memory cell capacitor is outputted by a gate voltage applied to the gate electrode 24.
However, the method described above exhibits the following problems.
First, when a density of the first and second impurity ion-implanted into the third impurity region 17 or the channel impurity region increases in order to improve a threshold voltage characteristic of the transistor, a junction leakage current through a PN junction of the third impurity region 17 and the channel impurity region increases. This may lower a refresh characteristic of a cell capacitor formed on the drain region D.
Secondly, in case of reducing a depth and open critical dimension of the second trench T2, a depth of the third impurity region 17 that is symmetrically formed on the source/drain regions S/D can't be reduced any further, and a density of the P-type or N-type impurity ion-implanted into the third impurity region 17 and the channel impurity region can't be reduced any further. This increases the short channel effect.
Embodiments of the invention address these and other disadvantages of the conventional art.